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Orchestre le développement SystemVerilog/RTL : planifie, génère, vérifie et itère en utilisant des agents spécialisés pour livrer un RTL fonctionnel, propre au lint et testé.
GF est l'orchestrateur principal pour le développement SystemVerilog (SV). Il coordonne la planification, la génération parallèle, le linting, la simulation, le débogage et le refactoring en routant le travail vers des sous-agents spécialisés (sv-planner, sv-orchestrator, gf-lint, gf-sim, sv-debug, sv-refactor). L'objectif est de livrer un RTL vérifié — et pas seulement du code d'exemple.
Utilisez GF lorsque vous devez créer, tester, corriger ou vérifier des modules RTL (FIFO, UART, AXI, machines à états, etc.), lorsque vous souhaitez une trace d'audit des étapes de l'agent, ou lorsque vous avez besoin d'un flux de travail basé sur la planification et les tests pour le code matériel. Privilégiez-le pour les conceptions multi-composants ou multi-fichiers où l'orchestration et le travail parallèle permettent de gagner du temps.
Agents compatibles déduits : sous-agents GateFlow (sv-planner, sv-orchestrator, sv-codegen), gf-lint, gf-sim, sv-debug, sv-refactor.
GateFlow GF is a SystemVerilog/RTL development orchestrator skill that routes tasks through specialist sub-agents (planner, codegen, debug, refactor, verification) with structured result parsing and retry loops. It has no bundled scripts. The SKILL.md is extensive (~30KB) with well-defined orchestration loops, decision tables, and error translation dictionaries. Security is clean — no credential leaks, destructive commands, or suspicious network calls. The skill relies on sub-agent spawning patterns that are framework-specific (gateflow: prefix) which limits portability.
Well-structured orchestration skill for hardware design. The symlink structure means the actual skill content lives under plugins/gateflow/ rather than skills/gf/. No security concerns. Uses allowed-tools restriction (Grep, Glob, Read, Write, Edit, Bash) which is good practice. The AskUserQuestion tool reference is Claude Code-specific. Niche audience (SystemVerilog/RTL developers) limits broad usefulness.
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