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Orchestrates SystemVerilog/RTL development: plan, generate, verify, and iterate using specialist agents to deliver working, lint-clean, tested RTL.
GF is the primary orchestrator for SystemVerilog (SV) development. It coordinates planning, parallel generation, linting, simulation, debugging, and refactoring by routing work to specialist sub-agents (sv-planner, sv-orchestrator, gf-lint, gf-sim, sv-debug, sv-refactor). The goal is delivered, verified RTL — not just example code.
Use GF when you need to create, test, fix, or verify RTL modules (FIFO, UART, AXI, state machines, etc.), when you want an audit trail of agent steps, or when you need a plan-first, test-first workflow for hardware code. Prefer it for multi-component or multi-file designs where orchestration and parallel work save time.
Inferred compatible agents: GateFlow subagents (sv-planner, sv-orchestrator, sv-codegen), gf-lint, gf-sim, sv-debug, sv-refactor.
GateFlow GF is a SystemVerilog/RTL development orchestrator skill that routes tasks through specialist sub-agents (planner, codegen, debug, refactor, verification) with structured result parsing and retry loops. It has no bundled scripts. The SKILL.md is extensive (~30KB) with well-defined orchestration loops, decision tables, and error translation dictionaries. Security is clean — no credential leaks, destructive commands, or suspicious network calls. The skill relies on sub-agent spawning patterns that are framework-specific (gateflow: prefix) which limits portability.
Well-structured orchestration skill for hardware design. The symlink structure means the actual skill content lives under plugins/gateflow/ rather than skills/gf/. No security concerns. Uses allowed-tools restriction (Grep, Glob, Read, Write, Edit, Bash) which is good practice. The AskUserQuestion tool reference is Claude Code-specific. Niche audience (SystemVerilog/RTL developers) limits broad usefulness.
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