from gateflow-plugin66
Orchestrates SystemVerilog/RTL development: plan, generate, verify, and iterate using specialist agents to deliver working, lint-clean, tested RTL.
GF is the primary orchestrator for SystemVerilog (SV) development. It coordinates planning, parallel generation, linting, simulation, debugging, and refactoring by routing work to specialist sub-agents (sv-planner, sv-orchestrator, gf-lint, gf-sim, sv-debug, sv-refactor). The goal is delivered, verified RTL — not just example code.
Use GF when you need to create, test, fix, or verify RTL modules (FIFO, UART, AXI, state machines, etc.), when you want an audit trail of agent steps, or when you need a plan-first, test-first workflow for hardware code. Prefer it for multi-component or multi-file designs where orchestration and parallel work save time.
Inferred compatible agents: GateFlow subagents (sv-planner, sv-orchestrator, sv-codegen), gf-lint, gf-sim, sv-debug, sv-refactor.
This skill has not been reviewed by our automated audit pipeline yet.
