Agent Skills

GF — SystemVerilog Orchestrator

gateflow-plugin

Orchestrates SystemVerilog/RTL development: plan, generate, verify, and iterate using specialist agents to deliver working, lint-clean, tested RTL.

CDC & Structural Analysis Tool Profiles

rtl-agent-team

Profiles and conventions for clock-domain crossing (CDC) and structural analysis tools (svlens, spyglass, vc_cdc, questa) plus normalized result fields for CI a

Design for Test (DFT)

digital-chip-design-agents

Guides Design-for-Test workflows: scan architecture planning, scan insertion, ATPG pattern generation, MBIST/LBIST insertion, JTAG setup, and DFT sign-off for m

μArch-to-Verify Policy (Phase 4→5)

rtl-agent-team

Reference policy and checklists defining artifact and quality gates, retry rules, and escalation for the RTL→Verification (Phase 4→5) pipeline in hardware verif

HoloCube Pomodoro & Trackers

holoclawd-open-firmware

Run a HoloCube-focused Pomodoro app with live water/exercise/focus/pills trackers; control sessions via the included example script and terminal commands.

nhero — Aftermarket Dispenser Network

asi

Framework treating pill dispensers as network devices: routing, access control, scramble-indexing and confidential supply tracking for custom dispenser workflow

Logic Synthesis — RTL to Gate-level Netlist

digital-chip-design-agents

Guidance and orchestration rules for logic synthesis: SDC constraint setup, compile strategies, netlist QC and LEC verification for ASIC/FPGA flows.