Agent Skills

GF — SystemVerilog Orchestrator

gateflow-plugin

Orchestrates SystemVerilog/RTL development: plan, generate, verify, and iterate using specialist agents to deliver working, lint-clean, tested RTL.

CDC & Structural Analysis Tool Profiles

RTL Agent Team

Profiles and conventions for clock-domain crossing (CDC) and structural analysis tools (svlens, spyglass, vc_cdc, questa) plus normalized result fields for CI a

μArch-to-Verify Policy (Phase 4→5)

RTL Agent Team

Reference policy and checklists defining artifact and quality gates, retry rules, and escalation for the RTL→Verification (Phase 4→5) pipeline in hardware verif

RTL Architecture Review

RTL Agent Team

Conducts read-only architecture reviews of RTL against microarchitecture specs to ensure timing, area, and power feasibility.