This skill provides a comprehensive verification layer for analog IC design workflows. It ensures that deterministic gates (like PDK compliance, corner margin checks, and layout geometry) are not only passed by scripts but also logically sound through AI-driven judgment.
Activate this skill after an analog_one_shot_runner has emitted outputs (A1-A9), or when you need to verify specific analog hardmacros, review analog corners, or perform silicon-realism checks on specifications.
skill_compliance_check.py to ensure output quality.Designed for agents integrated with the MCP-EDA ecosystem and IC design toolchains.
This skill has not been reviewed by our automated audit pipeline yet.