Agent Skills

Extract Circuit Netlist Edge Features

autoskill

Extract structured edge features from a bipartite circuit netlist (NetworkX MultiGraph), normalizing device/net ordering, mapping terminal colors, and detecting

Logic Synthesis — RTL to Gate-level Netlist

digital-chip-design-agents

Guidance and orchestration rules for logic synthesis: SDC constraint setup, compile strategies, netlist QC and LEC verification for ASIC/FPGA flows.