
from digital-chip-design-agents154
Guidance and orchestration rules for logic synthesis: SDC constraint setup, compile strategies, netlist QC and LEC verification for ASIC/FPGA flows.
This skill provides a comprehensive domain guide and orchestration rules for logic synthesis from RTL to a sign-off gate-level netlist. It specifies invocation behavior, pre-run context files to consult, supported EDA tools (Yosys, Synopsys DC, Cadence Genus), stage-by-stage rules (constraint setup, compile exploration, final compile, netlist QC) and required outputs for handoff to place-and-route.
Designed for complex agent orchestrators that can read/write repo memory files and run EDA tools or call external toolchains (orchestrator-capable agents, CI automation).
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