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from digital-chip-design-agents161
Automates multi-corner constraint validation, setup/hold analysis, and ECO guidance for digital chip design timing closure.
This skill provides a rigorous framework for performing Static Timing Analysis (STA) on digital chip designs. It automates the process of verifying that a design meets its timing requirements across multiple PVT (Process, Voltage, Temperature) corners, ensuring the chip operates reliably at the target frequency.
Activate this skill when you need to run timing analysis, review timing violations (WNS/TNS), validate SDC constraints, or generate Engineering Change Orders (ECOs) to fix setup and hold violations before tape-out.
Designed for specialized digital chip design agents and EDA tool orchestrators.
This skill has not been reviewed by our automated audit pipeline yet.
Design for Test (DFT)
Guides Design-for-Test workflows: scan architecture planning, scan insertion, ATPG pattern generation, MBIST/LBIST insertion, JTAG setup, and DFT sign-off for m
Logic Synthesis — RTL to Gate-level Netlist
Guidance and orchestration rules for logic synthesis: SDC constraint setup, compile strategies, netlist QC and LEC verification for ASIC/FPGA flows.
Scientific Exploratory Data Analysis
Human-guided, defensive exploratory data analysis for scientific datasets: capture context first, propose one step, run disposable scripts, and keep an append-o
Design for Test (DFT)
Guides Design-for-Test workflows: scan architecture planning, scan insertion, ATPG pattern generation, MBIST/LBIST insertion, JTAG setup, and DFT sign-off for m
CSV Data Summarizer
Automatically inspects CSV files and returns comprehensive statistical summaries and relevant visualizations using pandas and matplotlib/seaborn.
Logic Synthesis — RTL to Gate-level Netlist
Guidance and orchestration rules for logic synthesis: SDC constraint setup, compile strategies, netlist QC and LEC verification for ASIC/FPGA flows.