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Translates top-level system specifications into detailed per-block specifications for analog/mixed-signal circuit design.
This skill provides a structured framework for the 'upstream' phase of analog chip design. It allows an agent to translate high-level system requirements (like SNR, ENOB, and power constraints) into a feasible, closed set of specifications for individual circuit blocks.
Use this skill when planning the architecture of receiver front-ends, data-converter front-ends, sensor AFEs, PLLs/clocks, or PMICs. It is specifically designed for the phase before actual circuit design begins, where budgeting for noise, linearity, power, and area is critical.
Designed for agents capable of running Python (NumPy, scikit-rf) and EDA tools like ngspice or Xyce for behavioral verification.
This skill has not been reviewed by our automated audit pipeline yet.
Scientific Exploratory Data Analysis
Human-guided, defensive exploratory data analysis for scientific datasets: capture context first, propose one step, run disposable scripts, and keep an append-o
Design for Test (DFT)
Guides Design-for-Test workflows: scan architecture planning, scan insertion, ATPG pattern generation, MBIST/LBIST insertion, JTAG setup, and DFT sign-off for m
CSV Data Summarizer
Automatically inspects CSV files and returns comprehensive statistical summaries and relevant visualizations using pandas and matplotlib/seaborn.
Logic Synthesis — RTL to Gate-level Netlist
Guidance and orchestration rules for logic synthesis: SDC constraint setup, compile strategies, netlist QC and LEC verification for ASIC/FPGA flows.
Static Timing Analysis (STA)
Automates multi-corner constraint validation, setup/hold analysis, and ECO guidance for digital chip design timing closure.
ngspice Circuit Simulation Guide
Comprehensive guide for writing, editing, and simulating circuits using ngspice, covering netlists, control scripting, and Monte Carlo analysis.
Analog Output Verification
Spot-checks analog circuit simulation coverage, hardmacro completeness, and HIL data fidelity for IC design.