MCP App StoreMCP App Store
from digital-chip-design-agents161
Guides Design-for-Test workflows: scan architecture planning, scan insertion, ATPG pattern generation, MBIST/LBIST insertion, JTAG setup, and DFT sign-off for m
Provides a structured DFT orchestration skill that guides chip designers through scan architecture, scan insertion, ATPG pattern generation, MBIST/LBIST insertion, JTAG boundary-scan setup, and final sign-off. It encodes domain rules, DFT IO requirements, QoR metrics, stage outputs, and artifact lists so an orchestrator or engineer can run each stage reliably and produce required deliverables (scan netlist, pattern files, BSDL, sign-off reports).
Use this skill when planning or executing testability for an ASIC/SoC: defining scan chain architecture, inserting scan cells, running ATPG, adding memory BIST, configuring JTAG, or preparing DFT sign-off reports prior to tapeout or manufacturing test. Also used by orchestrator agents to provide stage rules and validation checks.
Best suited for engineering orchestration agents and code-assistant agents that can run Bash/Read/Write operations in EDA contexts and integrate with ATPG/EDA toolchains (e.g., Codex/Copilot-style agents that can call toolchain wrappers).
DFT (Design for Test) skill for chip design workflows — covers scan architecture, scan insertion, ATPG, BIST, JTAG setup, and sign-off. Well-structured domain guidance with clear stages, rules, QoR metrics, and output requirements. No scripts included; purely instructional. No security concerns — no network calls, credentials, or destructive commands. Very niche audience (VLSI/DFT engineers) limits broad usefulness.
Well-crafted domain skill for a niche hardware engineering audience. Clean security posture with no scripts or network dependencies. Would benefit from example scripts or templates for common DFT tasks.
Logic Synthesis — RTL to Gate-level Netlist
Guidance and orchestration rules for logic synthesis: SDC constraint setup, compile strategies, netlist QC and LEC verification for ASIC/FPGA flows.
Static Timing Analysis (STA)
Automates multi-corner constraint validation, setup/hold analysis, and ECO guidance for digital chip design timing closure.
Starlark Dev
Create, debug, and test Kurtosis Starlark packages — write package structure, run dry-runs, and inspect plan execution for reliable orchestration.
Run Execute
Orchestrates execution of work items across modes (autopilot, confirm, validate) with scripted init/complete tooling, plan/test/report artifacts and strict gati
Alpha Forge Pre-Ship Quality Gates
Pre-merge quality gates for PRs that validate RNG determinism, forked URLs, runtime parameter ranges, and manifest synchronization to reduce review cycles.
OpenTestAI
Automated, high-confidence AI testing: bug detection, persona feedback, and prioritized test-case generation using many specialized tester profiles.
Blender Build-Go (bgo)
Automate build → remove → install → enable → launch cycle for Blender extensions or add-ons to speed up iteration and CI workflows.
Overnight — Autonomous Long-Running Coding
Orchestrates long-running coding goals: decomposes objectives into atomic tasks, dispatches isolated worktree workers, verifies acceptance criteria, and merges
EventKit Integration (iOS/macOS)
Expert EventKit patterns for iOS/macOS: permissions, bidirectional sync, zero-width identity signatures, batch operations, and zombie-task handling.
Evolve — Goal-Driven Improvement Loop
Autonomous improvement loop that selects high-value work, runs a full research-plan-implement (/rpi) cycle, validates changes, and repeats to compound repo impr