Design for Test (DFT)

What it does

Provides a structured DFT orchestration skill that guides chip designers through scan architecture, scan insertion, ATPG pattern generation, MBIST/LBIST insertion, JTAG boundary-scan setup, and final sign-off. It encodes domain rules, DFT IO requirements, QoR metrics, stage outputs, and artifact lists so an orchestrator or engineer can run each stage reliably and produce required deliverables (scan netlist, pattern files, BSDL, sign-off reports).

When to use it

Use this skill when planning or executing testability for an ASIC/SoC: defining scan chain architecture, inserting scan cells, running ATPG, adding memory BIST, configuring JTAG, or preparing DFT sign-off reports prior to tapeout or manufacturing test. Also used by orchestrator agents to provide stage rules and validation checks.

What's included

• Scripts: none bundled in-skill (has_scripts=false).
• References: none in-skill, but the skill expects memory files and repo-level pipeline orchestration references.
• Instructions: detailed stage-by-stage rules (dft_architecture, scan_insertion, atpg, bist_insertion, jtag_setup, dft_signoff), QoR metrics, constraint defaults, and memory/write patterns for run state and experiences.

Compatible agents

Best suited for engineering orchestration agents and code-assistant agents that can run Bash/Read/Write operations in EDA contexts and integrate with ATPG/EDA toolchains (e.g., Codex/Copilot-style agents that can call toolchain wrappers).